EE Herald

Vendor independent HDL code for image processing using FPGA/ ASICs

The design framework inside the toolbox supports multiple interface types, frame sizes, and frame rates, including high-definition (1080p) video. HDL implementations supporting architecture process ...
EDN

Product how-to: Achieving STARC and DO-254 compliance using HDL Coder-generated code

HDL Coder generates target independent, synthesizable Verilog and VHDL code from MATLAB functions, Simulink models, and Stateflow charts. The generated HDL code is bit-true and cycle-accurate to ...
Hackaday

Learning Verilog For FPGAs: Hardware At Last!

Getting into FPGA design isn’t a monolithic experience. You have to figure out a toolchain, learn how to think in hardware during the design, and translate that into working Verliog. The end goal is ...
Design-Reuse

A Real-Time Image Processing with a Compact FPGA-Based Architecture

In this paper we present a filed programmable gate array implementation of a real time video smoothing algorithm. In comparison with smoothing video techniques like deblocking filters in H.264 or ...
Hackaday

Learning Verilog For FPGAs: The Tools And Building An Adder

Over the last year we’ve had several posts about the Lattice Semiconductor iCEstick which is shown below. The board looks like an overgrown USB stick with no case, but it is really an FPGA development ...
Design-Reuse

A practical approach to reusing HDL code in FPGA designs

From the very first day that you learn a new hardware description language (HDL), you reuse code. Initially, this might involve copying an example and modifying it in order to learn and expand your ...
EDN

Efficient Testing of Analog/Mixed-Signal ICs using Verilog-A

Nitin Mohan received his B.Tech. in Electronics Engineering from Institute of Technology-BHU, India in 1999 and MA.Sc. in Electrical and Computer Engineering from University of Waterloo, Canada in ...